1. Field of the Invention
The present invention relates to a method for forming the contact openings in a multi-layer structure and, more particularly, to a method that reduces overetching of the top conductive structure during the formation of the contact openings.
2. Description of the Related Art
Prior to the formation of a first metal layer, conventional semiconductor devices are covered with a layer of insulation material that is formed to have a more planarized top surface than the underlying topography of the semiconductor device. The overlying layer of insulation material, in turn, isolates the semiconductor device from the outside world and provides the support structure needed for the to-be-formed metal lines.
FIG. 1 shows a cross-sectional diagram that illustrates a portion of a conventional semiconductor device 30. As shown in FIG. 1, semiconductor device is formed on a substrate 20 that includes a 30 conductive region 22 such as a source or drain region.
The semiconductor device 30, in turn, is covered with a layer of insulation material 40, and has a plurality of layers that include a poly-2 layer 32, a poly-1 layer 34, and an interpoly dielectric layer 36, such as ONO, formed between the poly-1 and poly-2 layers 32 and 34. In addition, poly-2 layer 32, poly-1 layer 34, and conductive region 22 are electrically connected to metal lines M1, M2, and M3 by contacts C1, C2, and C3, respectively.
As further shown in FIG. 1, the underlying topography of semiconductor device 30, which is defined on the top by poly-2 layer 32, in the middle by poly-1 layer 34, and at the bottom by conductive region 22, has a substantial variation in height.
On the other hand, the topography of the top surface of the layer of insulation material 40, while not being substantially planar, smoothes out the changes in height from the poly-2 layer 32 to the poly-1 layer 34, and from the poly-1 layer 34 to the surface of substrate 20. Any one of several well-known processes, which include the use of spin-on-glass (SOG), reflow, and resist etchback, can be used to form the more planarized top surface of the layer of insulation material 40.
One significant advantage that results from the surface of the layer of insulation material 40 not being substantially planarized is that the depths of contacts C1, C2, and C3 are roughly similar. As a result, neither poly-2 layer 32, poly-1 layer 34, nor substrate 20 is subject to severe overetching during the formation of the contact openings.
More recently, however, as a result of shrinking design rules (0.35 micron technology) and the use of more metal interconnect layers, the above-noted techniques that have been conventionally utilized to form the layer of insulation material are giving way to a planarization technique known as chemical mechanical polishing (CMP). With CMP, a layer of insulation material is formed over the semiconductor device, and then polished down to a fully planar surface.
FIG. 2 shows a cross-sectional drawing that illustrates the semiconductor device 30 of FIG. 1 with a chemically mechanically polished insulation layer 50. As shown in FIG. 2, one major problem caused by CMP techniques is that the depths of contacts C1, C2, and C3 are no longer roughly similar, but are instead significantly different.
As a result, when the layer of insulation material 50 is etched to form the contact openings C1, C2, and C3, the insulation layer 50 and the poly-2 layer 32 are severely overetched by the time a contact opening is made to the conductive region 22 of substrate 20. Overetching of the insulation layer 50 varies the diameters of the contact openings, while overetching of the poly-2 layer 32 varies the electrical characteristics of the device.
One technique for limiting the overetching is to use two contact masks; one mask for the shallow contacts and one mask for the deep contacts. Although this technique reduces the problem of overetching, it requires an additional masking step that increases the cost and complexity of the process.
Another technique that can be utilized to limit the overetching is to form a portion of the poly-2 layer 32 on the same level as the poly-1 layer 34. FIG. 3 shows a cross-sectional drawing that illustrates the semiconductor device 30 of FIG. 1 with a portion of the poly-2 layer 32 formed at the same level as poly-1 layer 34.
As shown in FIG. 3, by forming a portion of the poly-2 layer on the same level, the etching time required to expose both the poly-2 and poly-1 layers 32 and 34 is approximately the same. As a result, the poly-2 and poly-1 layers 32 and 34 will only be slightly overetched during the additional etch time required to expose the conductive substrate region (not shown in FIG. 3). The drawback to this approach, however, is that by forming the poly-2 layer 32 on the same level as the poly-1 layer 34, the size of the die must often be increased to accommodate the larger size of the poly-2 layer.
Thus, there is a need for a method that can form contact openings in a planarized layer of insulation material without overetching the layer of insulation material or the underlying conductive structures, requiring additional masking steps, or increasing the die size.